1. Field of the Invention
The invention relates generally to the fabrication of semiconductor devices and to polishing and planarizing of substrates.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large-scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
Multilevel interconnects are formed by the sequential deposition and removal of materials from the substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarizing a surface, or xe2x80x9cpolishingxe2x80x9d a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material and in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing media in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing media. The substrate and polishing media are moved in a relative motion to one another.
A polishing composition is provided to the polishing media to effect chemical activity in removing material from the substrate surface. The polishing composition may contain abrasive material to enhance the mechanical activity between the substrate and polishing media. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing media while dispersing a polishing composition to effect both chemical activity and mechanical activity. The chemical and mechanical activity removes excess deposited materials as well as planarizing a substrate surface.
Chemical mechanical polishing may be used in the fabrication of shallow trench isolation (STI) structures. STI structures that may be used to separate transistors and components of a transistor, such as source/drain junctions or channel stops, on a substrate surface during fabrication. STI structures can be formed by depositing a series of dielectric materials and polishing the substrate surface to remove excess or undesired dielectric materials. An example of a STI structure includes depositing a silicon nitride layer on an oxide layer formed on a silicon substrate surface, patterning and etching the substrate surface to form a feature definition, depositing a silicon oxide fill of the feature definitions, and polishing the substrate surface to remove excess silicon oxide to form a feature. The silicon nitride layer may perform as a hard mask during etching of the features in the substrate and/or as a polishing stop during subsequent polishing processes. Such STI fabrication processes require polishing the silicon oxide layer to the silicon nitride layer with a minimal amount of silicon nitride removed during the polishing process in order to prevent damaging of the underlying materials, such as oxide and silicon.
The STI substrate is typically polished using a conventional polishing media and an abrasive containing polishing slurry. However, polishing STI substrates with conventional polishing pads and abrasive containing polishing slurries has been observed to result in overpolishing of the substrate surface and form recesses in the STI features and other topographical defects such as microscratches on the substrate surface. This phenomenon of overpolishing and forming recesses in the STI features is referred to as dishing. Dishing is highly undesirable because dishing of substrate features may detrimentally affect device fabrication by causing failure of isolation of transistors and transistor components from one another resulting in short-circuits. Additionally, overpolishing of the substrate may also result in nitride loss and exposing the underlying silicon substrate to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
FIGS. 1A-1C are schematic diagrams illustrating the phenomena of dishing and nitride loss. FIG. 1A shows an example of one stage of the STI formation process with a silicon nitride layer 20 and thermal oxide layer 15 disposed and patterned on a substrate 10. A silicon oxide material 30 is deposited on the substrate surface in a sufficient amount to fill features 35.
FIG. 1B illustrates the phenomena of dishing observed with polishing by conventional techniques. During polishing of the silicon oxide material 30 to the silicon nitride layer 20, the silicon oxide material 30 may be overpolished and surface defects, such as recesses 40, may be formed in the silicon oxide material 30. The excess amount of silicon oxide material removed from overpolishing the substrate surface, represented by dashed lines, is considered the amount of dishing 50 of the feature.
FIG. 1C illustrates nitride loss from the surface of the silicon nitride layer 20 from excess polishing of the substrate surface with conventional polishing processes. Silicon nitride loss may take the form of excess removal of silicon nitride, or xe2x80x9cthinningxe2x80x9d of the silicon nitride layer, from the desired amount 60 of silicon nitride. The silicon nitride loss may render the silicon nitride layer 30 unable to prevent or limit damage to or contamination of the underlying substrate material during polishing or subsequent processing.
One proposed solution to reduce dishing and nitride loss is the use of pressure sensitive slurries, also known as non-Prestonian slurries. Prestonian slurries are broadly defined as slurries that have a removal rate proportional to both the contact pressure between the substrate and platen and the rotational speed of the platen. Non-Prestonian slurries have removal rates that are not proportional to the polishing pressure and the rotational speed. For example, a non-Prestonian slurry may have a linear correlation between removal rate and polishing pressure, but may reach a range of polishing pressures, typically at decreasing polishing pressures, which results in no noticeable removal of material from the substrate surface.
FIG. 2 shows a comparison between Prestonian slurry A, typically a conventional polishing slurry, and non-Prestonian slurry B. The Prestonian slurry A is shown with a polishing rate having a constant linear slope or removal rate versus polishing pressure (or rotational speed), while the non-Prestonian slurry B has a polishing rate with a variable linear slope during increasing polishing pressure. For example, in FIG. 1, the slope for Slurry B, has a first portion of a relatively consistent initial removal rate followed by a second portion of increasing removal rate with increasing polishing pressure, which then returns to a relatively consistent removal rate with further application of increasing polishing pressure.
It has been observed that the non-Prestonian slurries are insensitive to overpolishing and exhibit reduced or minimal dishing or nitride loss of substrate features. However, non-Prestonian slurries are often more expensive than Prestonian slurries and have relatively low polishing rates compared to Prestonian slurries, which result in increased production costs and reduced substrate throughput. Additionally, non-Prestonian slurries often produce substrate surfaces with more than a desirable number of microscratches and other topographical defects formed in the substrate surface. Microscratches are indentations formed in the substrate surfaces that are approximately 0.5 micron wide, 0.1 micron deep and from 10 to 50 microns in length. Microscratches can be detrimental to subsequent polishing processes and detrimentally affect process device yield, and thus, are highly undesirable.
Therefore, there exists a need for a method and polishing composition that facilitates the removal of dielectric materials with minimal or reduced defect formation during polishing of a substrate surface.
Aspects of the invention generally provide a method and composition for planarizing a substrate surface with reduced or minimal defects in surface topography and reduced processing times. In one aspect, a method is provided for processing a substrate including positioning a substrate comprising at least first dielectric material and second dielectric material disposed thereon in a polishing apparatus having polishing media disposed thereon, polishing the substrate with a first polishing composition having a first selectivity, and polishing the substrate with a second polishing composition having a second selectivity greater than the first selectivity.
In another aspect, a method is provided for processing a substrate including positioning a substrate comprising at least first dielectric material and second dielectric material disposed thereon in a polishing apparatus having polishing media disposed thereon, polishing the substrate with a first polishing composition having a first selectivity, and polishing the substrate with a second polishing composition having a second selectivity less than the first selectivity.
In another aspect, a method for processing a substrate is provided including providing a substrate having at least first dielectric material and second dielectric material disposed thereon in a polishing apparatus, polishing the substrate on a first platen with a first polishing composition comprising a removal rate ratio of the first dielectric material and the second dielectric material between about 1:1 and about 5:1, polishing the substrate on a second platen with a second polishing composition, and polishing the substrate on a third platen with a third polishing composition comprising a removal rate ratio of the first dielectric material and the second dielectric material of about 30:1 or greater.
In another aspect, a method is provided for processing a substrate including providing a substrate having at least first dielectric material and second dielectric material disposed thereon in a polishing apparatus, polishing the substrate on a first platen with a first polishing composition comprising a removal rate ratio of the first dielectric material and the second dielectric material of about 30:1 or greater, polishing the substrate on a second platen with a second polishing composition, and polishing the substrate on a third platen with a third polishing composition comprising a removal rate ratio of the first dielectric material and the second dielectric material between about 1:1 and about 5:1.